Synaptic and neural behaviours in a standard silicon transistor – Nature
Mehonic, A. & Kenyon, A. J. Brain-inspired computing needs a master plan. Nature 604, 255–260 (2022).
Google Scholar
Orchard, G. et al. Efficient neuromorphic signal processing with Loihi 2. In Proc. 2021 IEEE Workshop on Signal Processing Systems (SiPS) (eds Sousa, L. & Sheikh, F.) 254–259 (IEEE, 2021).
Cassidy, A. S. et al. 11.4 IBM NorthPole: an architecture for neural network inference with a 12 nm chip. In Proc. 2024 IEEE International Solid-State Circuits Conference (ISSCC) Vol. 67 (ed. O’Mahony, F.) 214–215 (IEEE, 2024).
Kumar, S., Wang, X., Strachan, J. P., Yang, Y. & Lu, W. D. Dynamical memristors for higher-complexity neuromorphic computing. Nat. Rev. Mater. 7, 575–591 (2022).
Google Scholar
Koch, C. Computation and the single neuron. Nature 385, 207–210 (1997).
Google Scholar
Li, C. et al. Short-term synaptic plasticity in emerging devices for neuromorphic computing. iScience 26, 106315 (2023).
Google Scholar
Editorial. Does AI have a hardware problem? Nat. Electron. 1, 205 (2018).
Google Scholar
Indiveri, G. et al. Neuromorphic silicon neuron circuits. Front. Neurosci. 5, 73 (2011).
Google Scholar
Merrikh-Bayat, F. et al. High-performance mixed-signal neurocomputing with nanoscale floating-gate memory cell arrays. IEEE Trans. Neural Netw. Learn. Syst. 29, 4782–4790 (2018).
Google Scholar
Song, W. et al. Programming memristor arrays with arbitrarily high precision for analog computing. Science 383, 903–910 (2024).
Google Scholar
Le Gallo, M. et al. A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nat. Electron. 6, 680–693 (2023).
Google Scholar
Amirsoleimani, A. et al. In-memory vector-matrix multiplication in monolithic complementary metal–oxide–semiconductor-memristor integrated circuits: design choices, challenges, and perspectives. Adv. Intell. Syst. 2, 2000115 (2020).
Google Scholar
Islam, R. et al. Device and materials requirements for neuromorphic computing. J. Phys. D Appl. Phys. 52, 113001 (2019).
Google Scholar
Pazos, S. et al. Solution-processed memristors: performance and reliability. Nat. Rev. Mater. 9, 358–373 (2024).
Google Scholar
Zhu, K. et al. Hybrid 2D–CMOS microchips for memristive applications. Nature 618, 57–62 (2023).
Google Scholar
Migliato Marega, G. et al. A large-scale integrated vector–matrix multiplication processor based on monolayer molybdenum disulfide memories. Nat. Electron. 6, 991–998 (2023).
Google Scholar
Sharma, D. et al. Linear symmetric self-selecting 14-bit kinetic molecular memristors. Nature 633, 560–566 (2024).
Han, J.-K. et al. Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware. Sci. Adv. 7, eabg8836 (2021).
Google Scholar
Woo, S. Y. et al. Low-power and high-density neuron device for simultaneous processing of excitatory and inhibitory signals in neuromorphic systems. IEEE Access 8, 202639–202647 (2020).
Google Scholar
Carrere, J.-P. et al. Embedded Flash memory thermal budget impact on core CMOS 90 nm devices. In Proc. ESSDERC 2007 – 37th European Solid State Device Research Conference (eds Schmitt-Landsiedel, D. & Thewes, R.) 263–266 (IEEE, 2007).
Chen, Y., Xiao, K., Qin, Y., Liu, F. & Wan, J. A compact artificial spiking neuron using a sharp-switching FET with ultra-low energy consumption down to 0.45 fJ/spike. IEEE Electron Device Lett. 44, 160–163 (2023).
Google Scholar
Dutta, S., Kumar, V., Shukla, A., Mohapatra, N. R. & Ganguly, U. Leaky integrate and fire neuron by charge-discharge dynamics in floating-body MOSFET. Sci. Rep. 7, 8257 (2017).
Google Scholar
Chavan, T., Dutta, S., Mohapatra, N. R. & Ganguly, U. Band-to-band tunneling based ultra-energy-efficient silicon neuron. IEEE Trans. Electron Devices 67, 2614–2620 (2020).
Google Scholar
Singh, A. K., Saraswat, V., Baghini, M. S. & Ganguly, U. Quantum tunneling based ultra-compact and energy efficient spiking neuron enables hardware SNN. IEEE Trans. Circuits Syst. I Regul. Pap. 69, 3212–3224 (2022).
Google Scholar
Kadam, A. A., Singh, A. K., Somappa, L., Baghini, M. S. & Ganguly, U. A compact low power multi-mode spiking neuron using band to band tunneling. In Proc. 2024 IEEE International Symposium on Circuits and Systems (ISCAS) (eds Nishio, Y. et al.) 1–5 (IEEE, 2024).
Boudou, A. & Doyle, B. S. Hysteresis I–V effects in short-channel silicon MOSFET’s. IEEE Electron Device Lett. 8, 300–302 (1987).
Google Scholar
Park, H. J., Bawedin, M., Choi, H. G. & Cristoloveanu, S. Kink effect in ultrathin FDSOI MOSFETs. Solid State Electron. 143, 33–40 (2018).
Google Scholar
Liang, F.-X., Wang, I.-T. & Hou, T.-H. Progress and benchmark of spiking neuron devices and circuits. Adv. Intell. Syst. 3, 2100007 (2021).
Google Scholar
Milozzi, A., Ricci, S. & Ielmini, D. Memristive tonotopic mapping with volatile resistive switching memory devices. Nat. Commun. 15, 2812 (2024).
Google Scholar
Ye, F., Kiani, F., Huang, Y. & Xia, Q. Diffusive memristors with uniform and tunable relaxation time for spike generation in event-based pattern recognition. Adv. Mater. 35, 2204778 (2023).
Google Scholar
Zucker, R. S. & Regehr, W. G. Short-term synaptic plasticity. Annu. Rev. Physiol. 64, 355–405 (2002).
Google Scholar
Chen, P.-Y., Peng, X. & Yu, S. NeuroSim+ : An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. In Proc. 2017 IEEE International Electron Devices Meeting (IEDM) (eds Rim, K. & Takayanagi, M.) 6.1.1–6.1.4 (IEEE, 2017).
Hochreiter, S. & Schmidhuber, J. Long short-term memory. Neural Comput. 9, 1735–1780 (1997).
Google Scholar
Moon, J. et al. Temporal data classification and forecasting using a memristor-based reservoir computing system. Nat. Electron. 2, 480–487 (2019).
Google Scholar
Fujiwara, H. et al. 34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 fully-digital compute-in-memory macro supporting INT12 × INT12 with a parallel-MAC architecture and foundry 6T-SRAM bit cell. In Proc. 2024 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 67 (ed. O’Mahony, F.) 572–574 (IEEE, 2024).
M1076 Analog Matrix Processor (Mythic, 2025); https://mythic.ai/products/m1076-analog-matrix-processor/.
Wen, T.-H. et al. Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing. Science 384, 325–332 (2024).
Google Scholar
Khan, F., Cartier, E., Woo, J. C. S. & Iyer, S. S. Charge trap transistor (CTT): an embedded fully logic-compatible multiple-time programmable non-volatile memory element for high-k-metal-gate CMOS technologies. IEEE Electron Device Lett. 38, 44–47 (2017).
Google Scholar
Embedded Flash IP Solutions (Infineon Technologies); www.infineon.com/cms/en/product/memories/embedded-flash-ip-solutions.
Lanza, M. et al. Memristive technologies for data storage, computation, encryption, and radio-frequency communication. Science 376, eabj9979 (2022).
Google Scholar
Cypress eCTTM Flash (Cypress Semiconductor Corporation, 2017); www.infineon.com/dgdl/Infineon-eCT_Flash-ProductBrief-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153137b2071.
Li, Y., Lee, J.-W. & Sze, S.-M. Optimization of the anti-punch-through implant for electrostatic discharge protection circuit design. Jpn. J. Appl. Phys. 42, 2152 (2003).
Google Scholar
Guegan, G. et al. A 0.10 μm buried p-channel MOSFET with through the gate boron implantation and arsenic tilted pocket. Solid State Electron. 46, 343–348 (2002).
Google Scholar
Takeuchi, H. et al. Punch-through stop doping profile control via interstitial trapping by oxygen-insertion silicon channel. IEEE J. Electron Devices Soc. 6, 481–486 (2018).
Google Scholar
Aguirre, F. et al. Hardware implementation of memristor-based artificial neural networks. Nat. Commun. 15, 1974 (2024).
Google Scholar
Qiao, S., Moran, S., Srinivas, D., Pamarti, S. & Iyer, S. S. Demonstration of analog compute-in-memory using the charge-trap transistor in 22 FDX technology. In Proc. 2022 International Electron Devices Meeting (IEDM) (eds Triyoso, D. & Moselund, K.) 2.5.1–2.5.4 (IEEE, 2022).
Xie, S. et al. 16.2 eDRAM-CIM: compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing. In Proc. 2021 IEEE International Solid-State Circuits Conference (ISSCC) Vol. 64 (ed. Ikeda, M.) 248–250 (IEEE, 2021).
Kim, S. et al. Neuro-CIM: a 310.4 TOPS/W neuromorphic computing-in-memory processor with low WL/BL activity and digital-analog mixed-mode neuron firing. In Proc. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (ed. Wong, P.) 38–39 (IEEE, 2022).
Pazos, S. et al. Synaptic and neural behaviours in a standard silicon transistor – dataset and simulation files. Zenodo https://doi.org/10.5281/zenodo.13843362 (2025).
Colinge, J.-P. Reduction of kink effect in thin-film SOI MOSFETs. IEEE Electron Device Lett. 9, 97–99 (1988).
Google Scholar
Moselund, K. E. et al. Punch-through impact ionization MOSFET (PIMOS): from device principle to applications. Solid State Electron. 52, 1336–1344 (2008).
Google Scholar
Park, S.-O., Jeong, H., Park, J., Bae, J. & Choi, S. Experimental demonstration of highly reliable dynamic memristor for artificial neuron and neuromorphic computing. Nat. Commun. 13, 2888 (2022).
Google Scholar
Bian, J. et al. Advances in memristor based artificial neuron fabrication-materials, models, and applications. Int. J. Extrem. Manuf. 6, 012002 (2023).
Google Scholar
Rauch, S. E. & Guarin, F. in Hot Carrier Degradation in Semiconductor Devices (ed. Grasser, T.) 29–56 (Springer, 2015).
Fair, R. B. & Sun, R. C. Threshold-voltage instability in MOSFET’s due to channel hot-hole emission. IEEE Trans. Electron Devices 28, 83–94 (1981).
Google Scholar
Saks, N. S. et al. Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique. IEEE Trans. Electron Devices 33, 1529–1534 (1986).
Google Scholar
Brisbin, D., Mirgorodski, Y. & Chaparala, P. Anomalous NMOSFET hot carrier degradation due to trapped positive charge in a DGO CMOS process. In Proc. 2005 IEEE International Reliability Physics Symposium (eds Volertsen, R. & Conley, J.) 269–274 (IEEE, 2005).
Yoshikawa, K. et al. Lucky-hole injection induced by band-to-band tunneling leakage in stacked gate transistors. In Proc. International Electron Devices Meeting – International Technical Digest on Electron Devices 577–580 (IEEE, 1990).
Ielmini, D., Ghetti, A., Spinelli, A. S. & Visconti, A. A study of hot-hole injection during programming drain disturb in Flash memories. IEEE Trans. Electron Devices 53, 668–676 (2006).
Google Scholar
